| 1. | Of course the sampling clock is itself a digital signal
时钟本身也是数字信号，也会干扰模拟电路。 |
| 2. | The sampling clock generator must also have adequate spectral purity
时钟发生电路固有的抖动应该足够小。 |
| 3. | Figure 5 . 36 shows the relationship between sampling clock jitter and snr previously presented
图5 . 36显示了采样时钟抖动和信噪比之间的关系。 |
| 4. | To achieve this the sampling clock should be isolated as much as possible from the noise present in the digital parts of the system
为此，时钟信号应该尽可能地与电路中强噪声的部分隔离开，例如数字电路。 |
| 5. | The adc aperture jitter must be minimal , and the sampling clock generated from a low phase - noise quartz crystal oscillator
Adc的孔径抖动必需尽可能的小，而且要使用低相位噪声的石英晶体振荡器作为采样时钟发生器。 |
| 6. | The ep2s15 of altera company , work as the system ’ s peripheral controller include fifo ( first in first out ) memory and sampling clock controller
Altera公司的ep2s15作为系统的外围控制器,实现对系统的fifo (先进先出存储器)与采样时钟的控制。 |
| 7. | In this paper design of some circuit including in a / d circuit is also analyzed , such as front analog circuit , sample clock circuit and data flip - latch circuit
同时对高速转换器件及转换电路中包括前端模拟电路、采样时钟、后端数据锁存等辅助电路设计进行了分析。 |
| 8. | As to phased array receiving , a scheme of separating the delay clock and sampling clock is explicated , which effectively enhance the phased receiving delay resolution
对于相控接收延时，本文阐述了一种将延时时钟和采样时钟分离的方案，有效地提高了接收延时分辨率。 |
| 9. | Those include power supply circuit design ; ground plane design and sample clock design . combining some radar development , its high - speed a / d circuit is tested , and has given out some test results
最后结合某雷达研制，对其高速模数转换电路设计进行了实际测试评估，并给出了部分测试结果。 |
| 10. | Such as harmonic distorted in front analog circuit , sample clock shaking , analog power and the noise in ground plane etc . some suggestion of circuit design is given to improve high - speed a / d circuit performance
在高速模数转换电路的应用设计中地电源供电设计、模数地平面设计、采样时钟设计等方面提出一些具有指导性的意见。 |
